A standard 24-transistor implementation of a static 1-bit full

Comparative Study of CMOS Full Adder Logic Styles

Karnaugh maps for Boolean function F1 and corresponding standard

Implementation of 1-bit Full Adder Circuit Using Pass Transistor Logic

Impact of multi threshold transistor in positive feedback source coupled logic (PFSCL) fundamental cell

Design of Low Power Fast Full Adder using Domino Logic Based on magnetic tunnel junction and Memristor

1-Bit Domino logic based half adder circuits.

And-Or-Invert Circuit: a) at the gate level, b) CMOS implementation, c)

PDF] A novel high-performance CMOS 1-bit full-adder cell

Multi-functional multi-gate one-transistor process-in-memory electronics with foundry processing and footprint reduction

Logic gate - Wikipedia